Lithography
There is an amazing amount of physics and technology advancements that
go into making logic and memory chips. I read this recent IEEE
Spectrum article about double patterning lithography.
Intel is already shipping mass production 45nm technology node chips,
and is planning to ship 32nm chips by end 2009. The definition of
technology node is the half pitch of metal lines of usually a memory
product, but it essentially gives an indication of the smallest
feature size in a chip. It is quite amazing to think that with the
various lithography tricks, manufacturers are able to obtain feature
sizes of under 45nm using 193nm wavelength light.
Lithography is probably not the most difficult problem faced by
integrated circuit manufacturers. Once they figure out EUV,
lithography probably won't be a problem until the end of scaling. At
these tiny dimensions, the transistors are extremely leaky. Electrons
simply tunnel through the gate dielectric. Quantum mechanical effects
are becoming dominant. Short channel effects. Parasitics are
degrading device performance, etc. It will be curious to see what
engineering tricks Intel, IBM etc. would come up with in the coming
years to ensure performance and density improvements in integrated
circuits.
